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8V34S208 revision a 06/26/14 1 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications data sheet 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 8V34S208 general description the 8V34S208 is a differential 1:8 lvds fanout buffer with a 2:1 input multiplexer. the device accepts dc to 250mhz clock and data signals and is designed for 1hz clock /1pps, 2khz and 8khz signal distribution. controlled by the input mode selection pin, the differential input stages accept both rectangular or sinusoidal signals. the 8V34S208 also provides level translated lvcmos/lvttl outputs which are copies of the individual differential inputs clka and clkb. the propagation delay of the device is very low, providing an ideal solution for clock distribution circuits with tight phase alignment requirements. the multiplexer select pin (sel) allows to select one out of two input signals, which is copied to the four differential outputs. features ? designed for 1pps, 2khz, 8khz and 10mhz gps clock signal distribution ? high speed 1:8 lvds fanout buffer ? eight differential lvds output pairs ? 2:1 input multiplexer ? two selectable differential inputs accept lvds and lvpecl signals ? accepts rectangular and sinusoidal input signals ? two input monitoring outputs (lvcmos) ? max output frequency: 250 mhz ? additive rms phase jitter: 118fs (typical) at 100mhz (12k-20mhz) ? part-to-part skew: 250ps (maximum) ? propagation delay: 325ps (typical), lvds output ? full 2.5v and 3.3v voltage supply ? -40c to 85c ambient operating temperature ? lead-free 32-lead vfqfn (rohs 6/6) packaging block diagram pin assignment 32-lead vfqfn 5mm x 5mm x 0.9mm nl package, epad top view
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 2 revision a 06/26/14 8V34S208 data sheet pin description and pin characteristic tables note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 1. pin descriptions number name type description 1 gnd power power supply ground. 2 clka input pulldown non-inverting differential clock input. 3 nclka input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 4 mode input pulldown input mode pin. see table 3b. lvcmos/lvttl interface levels. 5 sel input pulldown input selection pin. see table 3a. lvcmos/lvttl interface levels. 6 clkb input pulldown non-inverting differential clock input. 7 nclkb input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 8 svs input pulldown supply voltage select. see table 3c. lvcmos/lvttl interface levels. 9v ddo_b power output supply pin for qb output. 10 qb output single-ended qb clock output. lvcmos/lvttl interface levels. 11 gnd power power supply ground. 12 q0 output differential output pair. lvds interface levels. 13 nq0 output 14 q1 output differential output pair. lvds interface levels. 15 nq1 output 16 v dd power power supply pins for the device core 17 q2 output differential output pair. lvds interface levels. 18 nq2 output 19 q3 output differential output pair. lvds interface levels. 20 nq3 output 21 q4 output differential output pair. lvds interface levels. 22 nq4 output 23 q5 output differential output pair. lvds interface levels. 24 nq5 output 25 v dd power power supply pins for the device core 26 q6 output differential output pair. lvds interface levels. 27 nq6 output 28 q7 output differential output pair. lvds interface levels. 29 nq7 output 30 gnd power power supply ground. 31 qa output single-ended qa clock output. lvcmos/lvttl interface levels. 32 v ddo_a power output supply pin for qa output.
8V34S208 data sheet revision a 06/26/14 3 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications function tables table 2. pin characteristics symbol parameter test conditions minimum typical maximum units c in input capacitance mode, sel, svs 2 pf r pulldown pulldown resistor 50 k ? r pullup pullup resistor 50 k ? c pd power dissipation capacitance (per output) v dd, v ddo_a, v ddo_b = 3.465v 6 pf v dd, v ddo_a, v ddo_b = 2.625v 6 pf r out output impedance qa, qb v ddo_a, v ddo_b =3.3v5% 27 ? qa, qb v ddo_a, v ddo_b =2.5v5% 30 ? table 3a. input selection function table input outputs sel q[0:7], nq[0:7] qa qb 0 (default) clka clka clkb 1 clkb clka clkb table 3b. input mode function table 1 note 1: use a rectangular wave input for inputs with edge rate greater than 1v/ns. input operation mode clka, clkb 0 (default) inputs accept rectangular signals 1 inputs accept sinusoidal signals table 3c. supply voltage select function table input operation svs supply voltage 0 (default) set to logic 0 when v dd =v ddo_a =v ddo_b = 2.5v 1 set to logic 1 when v dd =v ddo_a =v ddo_b = 3.3v
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 4 revision a 06/26/14 8V34S208 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. note 1: according to jedec/jesd 22-a114/22-c101. dc electrical characteristics item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvcmos) outputs, i o (lvds) continuous current surge current -0.5v to v ddo_x + 0.5v 10ma 15ma maximum junction temperature, t j, max 125 c storage temperature, t stg -65 ? cto150 ? c esd - human body model 1 2000v esd - charged device model 1 1500v table 4a. power supply dc characteristics, v dd =v ddo_a =v ddo_b = 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo_a, v ddo_b lvcmos output supply voltage 3.135 3.3 3.465 v i dd power supply current 158 184 ma i ddo_a + i ddo_b lvcmos output supply current outputs unterminated 6 8 ma table 4b. power supply dc characteristics, v dd =v ddo_a =v ddo_b = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v v ddo_a, v ddo_b lvcmos output supply voltage 2.375 2.5 2.625 v i dd power supply current 150 174 ma i ddo_a + i ddo_b lvcmos output supply current outputs unterminated 5 8 ma
8V34S208 data sheet revision a 06/26/14 5 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications table 4c. lvcmos/lvttl dc characteristics, v dd =v ddo_a =v ddo_b = 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage 2.2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current sel, mode, svs v dd =v in = 3.465v 150 a i il input low current sel, mode, svs v dd = 3.465v, v in = 0v -10 a v oh output high voltage qa, qb i oh = -8ma 2.6 v v ol output low voltage qa, qb i ol = 8ma 0.5 v table 4d. lvcmos/lvttl dc characteristics, v dd =v ddo_a =v ddo_b = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage 1.8 v dd + 0.3 v v il input low voltage -0.3 0.6 v i ih input high current sel, mode, svs v dd =v in = 2.625v 150 a i il input low current sel, mode, svs v dd = 2.625v, v in = 0v -10 a v oh output high voltage qa, qb i oh = -8ma 1.8 v v ol output low voltage qa, qb i ol = 8ma 0.5 v table 4e. differential dc characteristics, v dd = 3.3v 5% or 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current clka, clkb, nclka, nclkb v dd =v in =v ddmax 150 a i il input low current clka, clkb v dd =v ddmax ,v in = 0v -10 a nclka, nclkb v dd =v ddmax ,v in = 0v -150 a v pp peak-to-peak voltage 1 note 1: v il should not be less than -0.3v and v ih should not be higher than v dd . 0.15 1.3 v v cmr common mode input voltage 1, 2 note 2: common mode input voltage is defined at the crosspoint. 1v dd ?(v pp /2) v table 4f. lvds differential dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 390 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.05 1.2 1.375 v ? v os v os magnitude change 50 mv
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 6 revision a 06/26/14 8V34S208 data sheet ac electrical characteristics table 4g. lvds differential dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 373 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.05 1.2 1.375 v ? v os v os magnitude change 50 mv table 5. ac characteristics, v dd =v ddo_a =v ddo_b = 3.3v 5% or 2.5v 5%, t a = -40c to 85c 1 symbol parameter test conditions minimum typical maximum units f out output frequency 250 mhz ? v/ ? t input edge rate 2 clka, clkb mode = 0 1 v/ns t pd propagation delay 3 clka, clkb to q[0-3], nq[0-3] 200 325 434 ps propagation delay 4 clka, clkb to qa, qb 970 1.20 1.62 ns t jit(?) buffer additive phase jitter, rms; refer to additive phase jitter section q[0-3], nq[0-3] f out = 156.25mhz, integration range: 12khz ? 20mhz, mode 0 118 170 fs tsk (pp) part-to-part skew 56 q[0-3], nq[0-3] 250 ps tsk (o) output skew 6 q[0-3], nq[0-3] 7 65 ps qa-qb 8 65 ps all outputs 1.3 ns tsk (p) pulse skew 9, 10 q[0-3], nq[0-3] 11 62 ps qa, qb 75 140 ps t r /t f output rise/ fall time qa, qb; 20% to 80% 200 350 ps q[0-3], nq[0-3] 20% to 80% 125 250 ps mux isolation mux isolation 11 f out = 100.00mhz, v pp = 400mv 53 db note 1: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 2: in mode = 1 sinusoidal input signals are permitted and no minimum input edge rate specification applies. note 3: measured from the differential input crosspoint to the differential output crosspoint using an input with 50% duty cycle. note 4: measured from the differential input crosspoint to the output at vddo_x/2 using an input with 50% duty cycle. note 5: defined a s skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cros spoints. note 6: this parameter is defined in accordance with jedec standard 65. note 7: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential crosspoints. note 8: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at vddo_x/2 of the output. note 9: output pulse skew t sk(p) is the absolute difference of the propagation delay times: | t plh ?t phl |. note 10: odc = input duty cycle (t sk(p) /2 * 1/output period) * 100 note 11: qx, nqx output measured differentially. see parameter measurement information for mux isolation diagram.
8V34S208 data sheet revision a 06/26/14 7 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications table 6. characteristics for 1pps operation, v dd = 3.3v 5% or v dd = 2.5v 5%, ta = -40c to 85c 1234 note 1: 1pps (one pulse per second) signals are defined as repetitive pulses with a rate (period) of 1hz. the positive input pulse width may vary. the active signal edge is the rising edge. parameters in this table are characterized for a positive input pulse width of 100ns, 100ms and 500ms; all device interfaces are dc-coupled. parameters are defined in accordance with itu-t g.703 amendment 1 - specifications for the physical layer of the itu-t g8271/y.1366 time synchronization interfaces. note 2: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 3: t pd ,t sk(o) ,t sk(p) and t sk(p) parameters of differential signals are referenced to the crosspoint. note 4: differential outputs for 1pps signal transmission are terminated balanced 100 ? according to the lvds output load test circuit figures. the dedicated 1pps outputs are the differential outputs q0-q3. symbol parameter test conditions minimum typical maximum units t input and output pulse period 1 s t p positive or negative pulse width 100 ns t pd propagation delay; clkx/nclkx to qx/nqx 300 650 ps tsk (p) pulse width distortion clkx/nclkx to qx/nqx 55 300 ps tsk (o) output skew 5 note 5: this parameter is defined in accordance with jedec standard 65. qx/nqx to qy/nqy 325 ps tsk (pp) part-to-part skew 6 note 6: defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. each device uses the same type of input. 350 ps t r /t f output rise/fall time 10% to 90% 50 150 350 ps
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 8 revision a 06/26/14 8V34S208 data sheet additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements have issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. measured using an rohde & schwarz sma100 as the input source. ssb phase noise (dbc/hz) offset from carrier frequency (hz)
8V34S208 data sheet revision a 06/26/14 9 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications parameter measurement information 2.5v lvds output load test circuit 2.5v core/2.5v lvcmos output load test circuit differential input level 3.3v lvds output load test circuit 3.3v core/3.3v lvcmos output load test circuit part-to-part skew v dd scope qx gnd -1.255% 1.25v5% v dd v ddo_a v ddo_b v dd gnd v cmr cross points v pp nclk[a:b] clk[a:b] gnd v dd scope qx gnd -1.65v5% 1.65v5% v dd v ddo_a v ddo_b t sk(pp) part 1 part 2 nqx qx nqx qx
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 10 revision a 06/26/14 8V34S208 data sheet parameter measurement information, continued lvds output skew differential propagation delay lvcmos output rise/fall time lvcmos output skew propagation delay lvds output rise/fall time nqx qx nqy qy t pd nclk[a:b] clk[a:b] nqx qx 20% 80% 80% 20% t r t f q[a:b] t sk(o) v ddo_x 2 v ddo_x 2 qx qy t pd v ddo_x 2 nclk[a:b] clk[a:b] q[a:b] 20% 80% 80% 20% t r t f v od nq[0:7] q[0:7]
8V34S208 data sheet revision a 06/26/14 11 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications parameter measurement information, continued differential pulse skew differential output voltage setup mux isolation pulse skew offset voltage setup t plh t phl tsk(p)= |t phl -t plh | nclk[a:b] clk[a:b] nqx qx amplitude (db) a0 spectrum of output signal q mux _isolation =a0?a1 (fundamental) frequency mux selects other input mux selects active input clock signal a1 t plh t phl tsk(p)= |t phl -t plh | v ddo_x 2 v ddo_x 2 nclk[a:b] clk[a:b] q[a:b]
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 12 revision a 06/26/14 8V34S208 data sheet applications information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 =v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a differential input to accept single-ended levels
8V34S208 data sheet revision a 06/26/14 13 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 3.3v differential clock input interface the clk /nclk accepts lvds, lvpecl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figure 2a to figure 2c show interface examples for the clk/nclk input with built-in 50 ? terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. clk/nclk input driven by a 3.3v lvpecl driver figure 2b. clk/nclk input driven by a 3.3v lvds driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver 3 . 3v c l k n c l k 3 . 3v 3 . 3v lvpe cl diff e r e nti a l in p u t 3.3v r1 100 lvds clk nclk 3.3v receiver zo=50 zo=50 clk nclk differential input lvpecl 3.3v zo=50 zo=50 3.3v r1 50 r2 50 r2 50
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 14 revision a 06/26/14 8V34S208 data sheet 2.5v differential clock input interface the clk /nclk accepts lvds, lvpecl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figure 3a to figure 3c show interface examples for the clk/nclk input with built-in 50 ? terminations driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. clk/nclk input driven by a 2.5v lvpecl driver figure 3b. clk/nclk input driven by a 2.5v lvds driver figure 3c. clk/nclk input driven by a 2.5v lvpecl driver c l k nc l k d i ffe r e nti a l i nput l vpe cl 2 . 5v zo = 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ?
8V34S208 data sheet revision a 06/26/14 15 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk/nclk input for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating there should be no trace attached.
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 16 revision a 06/26/14 8V34S208 data sheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 )of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 4a can be used with either type of output structure. figure 4b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. figure 4a. standard termination figure 4b. optional termination lvds driver z o ? z t z t lvds receiver lvds driver z o ? z t lvds receiver c z t 2 z t 2
8V34S208 data sheet revision a 06/26/14 17 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications power considerations ? lvds outputs this section provides information on power dissipation and junction temperature for the 8V34S208. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8V34S208 is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. the maximum current at 85c is as follows: i dd = 184ma i ddoa = 4ma i ddob = 4ma ? power (core, lvds) max =v dd_max *(i dd_max +i ddoa_max +i ddob_max ) = 3.465v * (184ma + 4ma + 4ma) = 665.28mw lvcmos output power dissipation ? dynamic power dissipation at 200mhz power (250mhz) = c pd * frequency * (v ddox_max ) 2 = 6pf * 250mhz * (3.465v) 2 = 18.01mw per output total cmos powe r=2* 18.01mw = 36.02mw total power_ max = 665.28mw + 36.02mw = 701.3mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 48.9c/w per ta b l e 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.701w * 48.9c/w = 119.29c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 32-lead vfqfn ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard test boards 48.9c/w 42.0c/w 39.4c/w
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 18 revision a 06/26/14 8V34S208 data sheet reliability information transistor count the transistor count for the 8V34S208 is: 492 table 8. ? ja vs. air flow table for a 32-lead vfqfn ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard test boards 48.9c/w 42.0c/w 39.4c/w
8V34S208 data sheet revision a 06/26/14 19 1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 32-lead vfqfn package outline and package dimensions
1:8 lvds fanout buffer with 2-input multiplexer for 1pps applications 20 revision a 06/26/14 8V34S208 data sheet ordering information table 9. ordering information part/order number marking package shipping packaging temperature 8V34S208nlgi idt8V34S208nlgi ?lead-free? 32-lead vfqfn tray -40 ? cto85 ? c 8V34S208nlgi8 idt8V34S208nlgi ?lead-free? 32-lead vfqfn tape & reel -40 ? cto85 ? c
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